Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide user-defined features. PLDs typically include various components, such as programmable logic cells, memory cells, digital signal processing cells, input/output cells, and other components. The PLD components may be interconnected through signal paths provided by routing wires of the PLD to implement a desired circuit design.
However, PLDs typically have a limited supply of routing wires available to interconnect components from different portions of the PLD. This differs from conventional application-specific integrated circuits (ASICs) in which empty physical spaces may be reserved to implement additional signal paths at a later time if desired. Thus, if a given circuit design requires too many signals to be interconnected between certain regions of a PLD, the limited number of available wires may become nearly or completely exhausted, leading to congestion in the PLD signal paths.
Existing approaches to determining PLD congestion are normally based on simplified representations of PLD routing wires. For example, in one approach, a PLD may be represented as having routing wires of uniform length. In another approach, a PLD may be represented as having equal numbers of routing wires with different lengths.
Unfortunately, such simplified representations typically do not account for actual PLD implementations which may include different numbers of routing wires having different lengths. As a result, signal congestion estimates obtained using such representations may differ substantially from the actual signal congestion exhibited by a PLD. Accordingly, there is a need for an improved approach to estimating signal congestion in PLDs.